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[VHDL-FPGA-Verilog] ram

Description: SRAM 静态存储器 vhdl代码 计算机组成原理-SRAM is a memory
Platform: | Size: 1024 | Author: 马三 | Hits:

[VHDL-FPGA-Verilog] Projeto

Description: Memory for cpu pepiline implements in vhdl a to duplicate ajuda na transgorm to jahe e na implementa ç ao da cpu de pieple
Platform: | Size: 183296 | Author: Juampi | Hits:

[Other] Design-Recipes-For-FPGAs

Description: 本书为VHDL教材，偏重于应用，主要内容包括图像与高速处理、嵌入式处理器、串行通信、数字滤波器、存储器、PS/2鼠标接口、PS/2键盘接口、VGA显示接口-Book VHDL textbook emphasis on the application, the main content including images and high-speed processing, embedded processors, serial communication, digital filters, memory, PS/2 mouse interface, PS/2 keyboard interface, VGA display interface
Platform: | Size: 11414528 | Author: James | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 先进先出存储器的接口设计，采用VHDL语言-FIFO memory interface design, using VHDL language
Platform: | Size: 2466816 | Author: 凯一 | Hits:

[Compress-Decompress algrithms] ahb2wishbone_latest.tar

Description: AHB to Wishbone memory interface VHDL source code
Platform: | Size: 10638336 | Author: cyf | Hits:

[VHDL-FPGA-Verilog] stack_16x8

Description: VHDL语言写的16x8堆栈模块设计，存储器全满时给出信号并拒绝继续存入；读出时按后进先出原则；存储数据一旦读出就从存储器中消失；有相应的testbech文件，经测试可用。对小型设计很有用！欢迎下载交流学习。-Write VHDL 16x8 stack module design, memory signal is given full and refused to continue the deposit readout LIFO principle store data read out from the memory disappear There are corresponding testbech file, tested available. Useful for small design! Welcome Download exchanges to learn.
Platform: | Size: 1024 | Author: 电工 | Hits:

[VHDL-FPGA-Verilog] dual

Description: DDR2双内存切换程序部分代码,用于VHDL的FPGA开发-DDR2 dual memory switching part of the program code for VHDL-FPGA development
Platform: | Size: 5120 | Author: joypoo | Hits:

[source in ebook] FIFO

Description: FPGA内部FIFO存储器设计的vHdl源代码-FPGA internal FIFO memory design vHdl source code
Platform: | Size: 1024 | Author: 罗智勇 | Hits:

[Communication] vhdl1

Description: 该程序实现了运用VHDL实现数字音频滤波，同时在FIR 滤波过程中减少了加法器和乘法器使用数量，大大减小了内存-The program implements the use of VHDL digital audio filtering, while in the FIR filtering process to reduce the number of adders and multipliers used, which greatly reduces the memory
Platform: | Size: 1374208 | Author: 张彬 | Hits:

[Other] method-Modelsim-simulation-library

Description: 以硬件描述语言（Verilog或VHDL）所完成的电路设计，可以经过简 单的综合与布局，快速的烧录至 FPGA 上进行测试，是现代 IC设计验证的技术主流。这些可编辑元件可以被用来实现一些基本的逻辑门电路（比如AND、OR、XOR、NOT）或者更复杂一些的组合功能比如解码器或数学方程式。在大多数的FPGA里面，这些可编辑的元件里也包含记忆元件例如触发器（Flip－flop）或者其他更加完整的记忆块。-A hardware description language (Verilog or VHDL) the completed circuit design, synthesis and layout through a simple and fast burn to the FPGA for testing, is the modern mainstream IC design verification techniques. These editable element can be used to implement some basic logic gates (such as AND, OR, XOR, NOT), or a combination of more complex functions such as decoders or mathematical equations. In most of the FPGA inside, these elements can be edited in memory elements such as flip-flops also includes (Flip-flop), or other more complete memory block.
Platform: | Size: 221184 | Author: 田海 | Hits:

[VHDL-FPGA-Verilog] MP3-coder

Description: In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder. Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read the output or input 576 frequency lines.-This folder contains three directories: Huffman, IMDCT and Filterbank, each of them includes all the VHDL source codes of the component.
Platform: | Size: 36864 | Author: 睿宸 | Hits:

[VHDL-FPGA-Verilog] control_1

Description: 在VHDL开发环境中，实现单片机的cpu的控制器，从存储器中逐条取指令，并进行译码，通过控制电路，完成各种指令操作-In VHDL development environment, to achieve single-chip controller cpu, one by fetching instructions from memory and decodes the control circuit, complete a variety of instruction
Platform: | Size: 3532800 | Author: 王碧琳 | Hits:

[Other] e001_vhdlsample

Description: VHDL 例程,包括寄存器,计数器,存储器,各种触发器,各种运算单元等的VHDL程序入门程序集锦.-VHDL routines, including VHDL entry procedures highlights program registers, counters, memory, various triggers, such as various arithmetic unit.
Platform: | Size: 168960 | Author: 刘志强 | Hits:

[VHDL-FPGA-Verilog] calc_16_01_14

Description: A VHDL code for a simple calculator.It reads the operator and operands form the memory and execute
Platform: | Size: 589824 | Author: Prasad.M | Hits:

[Embeded-SCM Develop] memoire_alphabet

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器。实现memory存储。-Altera NIOS processor experiments QUARTUS using VHDL compiler into processors. Achieving memory storage.
Platform: | Size: 1024 | Author: romMay | Hits:

[VHDL-FPGA-Verilog] lcd

Description: implementation of 16x2 lcd module driver in vhdl with the scroll a read facility.also a memory device is been also added.for 576 charecter in spartan 3 device tested.
Platform: | Size: 2048 | Author: arka | Hits:

[VHDL-FPGA-Verilog] a

Description: 简易电子琴演奏器的VHDL实现 本实验实现了简易的电子琴演奏，包括自动和手动演奏。 输入为BTN0~BTN6，代表1~7共7个音符。音高可切换低中高音，用两个拨码开关控制：“00”为低音，“10”或“01”为中音，“11”为高音。一个拨码开关切换收动/自动。一个开关控制存储（播放存储）/不存储。一个按键clr复位。 输出为8*8点阵、两个数码管（显示音高和字符）、蜂鸣器。 具体功能： 当切换至手动模式时，根据手动按键播放音乐并显示。此时若存储开关置1，当前播放音符被存储，采样频率10HZ。 当切换置自动模式时，播放系统自身存储的音乐。此时若存储开关置1，播放的是之前手动播放时存储的音乐。若再切换回手动模式，则音乐可以接上回位置继续往下存储。 当clr置1时，系统回到手动播放的等待状态，并将已存储的音乐清除。 -Simple keyboard player VHDL implementation of the experimental realization of a simple keyboard playing, including automatic and manual performance. Input BTN0 ~ BTN6, 1-7 behalf of seven notes. Alt switchable low pitch, with two DIP switches control: " 00" for the bass, " 10" or " 01" as the alto, " 11" for the treble. A closing move DIP switch/automatic. A switch control memory (memory playback)/not stored. A reset button clr. The output of 8* 8 dot matrix, two digital (display pitch and character), the buzzer. Specific feature: When switched to manual mode, according to the manual button to play music and display. At this point, if the memory switch is set to 1, the currently playing notes are stored, the sampling frequency 10HZ. When the automatic mode switch is set to play stored music system itself. At this point, if the memory switch is set to 1, the manual before playing stored music playback. Ruozai switch back to manual mode, you can connec
Platform: | Size: 5189632 | Author: carmack | Hits:

[VHDL-FPGA-Verilog] cache

Description: 利用VHDL语言，仿真cache与主存的关系，使用了类似数组的方法。-using vhdl,tell us the relation between cache and memory.
Platform: | Size: 336896 | Author: fq | Hits:

[VHDL-FPGA-Verilog] proje2

Description: it is code for implement the FIFO in VHDL. FIFO is first in first out memory.
Platform: | Size: 1024 | Author: Arash | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。-Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.
Platform: | Size: 822272 | Author: wang | Hits:
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